Next generation routers

As the broadband access technologies, such as DSL, cable modem, and gigabit Ethernet, are providing affordable broadband solutions to the Internet from home and the enterprise, it is required to build next generation routers with high-speed interfaces (e.g., 10 or 40 Gb/s) and large switching capaci...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Proceedings of the IEEE Jg. 90; H. 9; S. 1518 - 1558
1. Verfasser: Chao, H.J.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.09.2002
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithms
Architecture
Broadband
Buildings
Classification
Computer networks
DSL
Ethernet
Ethernet networks
Fabrics
Internet
IP (Internet Protocol)
Memory management
Modems
Packet switching
Routers
Routing (telecommunications)
Switches
Telecommunication traffic
ISSN:0018-9219, 1558-2256
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:As the broadband access technologies, such as DSL, cable modem, and gigabit Ethernet, are providing affordable broadband solutions to the Internet from home and the enterprise, it is required to build next generation routers with high-speed interfaces (e.g., 10 or 40 Gb/s) and large switching capacity (e.g., multipetabit). This paper first points out the issues of building such routers, such as memory speed constraint, packet arbitration bottleneck, and interconnection complexity. It then presents several algorithms/architectures to implement IP route lookup, packet classification, and switch fabrics. Some of the functions, such as packet classification, route lookup, and traffic management, can be implemented with emerging network processors that have the advantages of providing flexibility to new applications and protocols, shortening the design cycle and time-to-market, and reducing the implementation cost by avoiding the ASIC approach. Several proposed algorithms for IP route lookup and packet classification are compared in respect to their search/update speeds and storage requirements. Different efficient arbitration schemes for output port contention resolution are presented and analyzed. The paper also surveys various switch architectures of commercial routers and switch chip sets. At the end, it outlines several challenging issues that remain to be researched for next generation routers.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ObjectType-Article-2
ObjectType-Feature-1
content type line 23
ISSN:0018-9219
1558-2256
DOI:10.1109/JPROC.2002.802001