Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials

In this paper, we consider the design of bit-parallel canonical basis multipliers over the finite field GF(2 m ) generated by a special type of irreducible pentanomial that is used as an irreducible polynomial in the Advanced Encryption Standard (AES). Explicit formulas for the coordinates of the mu...

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Vydané v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 14; číslo 12; s. 1388 - 1393
Hlavní autori:	Imana, J.L., Hermida, R., Tirado, F.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Piscataway, NJ IEEE 01.12.2006 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Applied sciences Canonical basis Capacitance Circuit properties Complexity Cryptography Delay estimation Design engineering Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Filtering Galois fields Gates Hardware Hardware description languages Integrated circuit interconnections Integrated circuits Integrated circuits by function (including memories and processors) irreducible pentanomials Mathematical analysis matrix decomposition multiplication Multipliers Polynomials Runtime Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Timing Very large scale integration Finite field Hardware description languages Arithmetic circuit XOR circuit Logic gate irreducible pentanomials Parallel architectures Matrix decomposition Galois fields Logic circuit Coding AES algorithm Integrated circuit Canonical basis Multiplier multiplication
ISSN:	1063-8210, 1557-9999
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Popis
Shrnutí:	In this paper, we consider the design of bit-parallel canonical basis multipliers over the finite field GF(2 m ) generated by a special type of irreducible pentanomial that is used as an irreducible polynomial in the Advanced Encryption Standard (AES). Explicit formulas for the coordinates of the multiplier are given. The main advantage of our design is that some of the expressions obtained are common to any irreducible polynomial, so our multiplier can be generalized to perform the multiplication over general irreducible polynomials. Moreover, the obtained expressions can be easily converted to parameterizable code using hardware description languages. The theoretical complexity analysis also shows that our bit-parallel multipliers present a reduced number of xor gates with respect to the best known results found in the literature
Bibliografia:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 content type line 23
ISSN:	1063-8210 1557-9999
DOI:	10.1109/TVLSI.2006.887835