Synthesis method of high speed finite state machines

The paper is concerned with the problem of state assignment and logic optimization of high speed finite state machines. The method is designed for PAL-based CPLDs implementations. Determining the number of logic levels of the transition function before the state encoding process, and keeping the con...

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Veröffentlicht in:	Bulletin of the Polish Academy of Sciences. Technical sciences Jg. 58; H. 4; S. 635 - 644
Hauptverfasser:	Czerwiński, R., Kania, D.
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Warsaw Versita 01.12.2010 Polish Academy of Sciences
Schlagworte:	Complex Programmable Logic Devices (CPLD) Finite State Machines (FSM) logic optimization Programmable Array Logic (PAL) state assignment tri-state buffer
ISSN:	0239-7528, 2300-1917
Online-Zugang:	Volltext
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