Synthesis method of high speed finite state machines

The paper is concerned with the problem of state assignment and logic optimization of high speed finite state machines. The method is designed for PAL-based CPLDs implementations. Determining the number of logic levels of the transition function before the state encoding process, and keeping the con...

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Veröffentlicht in:Bulletin of the Polish Academy of Sciences. Technical sciences Jg. 58; H. 4; S. 635 - 644
Hauptverfasser: Czerwiński, R., Kania, D.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Warsaw Versita 01.12.2010
Polish Academy of Sciences
Schlagworte:
Complex Programmable Logic Devices (CPLD)
Finite State Machines (FSM)
logic optimization
Programmable Array Logic (PAL)
state assignment
tri-state buffer
ISSN:0239-7528, 2300-1917
Online-Zugang:Volltext
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Zusammenfassung:The paper is concerned with the problem of state assignment and logic optimization of high speed finite state machines. The method is designed for PAL-based CPLDs implementations. Determining the number of logic levels of the transition function before the state encoding process, and keeping the constraints during the process is the main problem at hand. A number of coding bits, as well as codes for the states, are adjusted to achieve a machine with a determined number of logic levels. Elements of two-level minimization are taken into consideration in the state assignment. The proposed optimization method is based on utilizing tri-state buffers, thus enabling achievement of a one-logic-level output block.
Bibliographie:ark:/67375/QT4-NMXC51X1-6
istex:482949CFB149167BD6B5FF09332445AFA79115D6
v10175-010-0067-6.pdf
ArticleID:v10175-010-0067-6
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ISSN:0239-7528
2300-1917
DOI:10.2478/v10175-010-0067-6