Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design

This paper presents the algorithm and reconfigurable architecture of motion-adaptive deinterlacer for high-definition video. The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture co-design methodology and Caltrop actor langu...

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Veröffentlicht in:Journal of signal processing systems Jg. 63; H. 2; S. 181 - 189
Hauptverfasser: Lee, Gwo Giun, Wang, Ming-Jiun, Chen, Bo-Han, Chen, JiunFu, Jao, Ping-Keng, Hsiao, Ching Jui, Wei, Ling-Fei
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Boston Springer US 01.05.2011
Schlagworte:
Algorithms
Architecture
Circuits and Systems
Co-design
Computer Imaging
Design engineering
Electrical Engineering
Engineering
Image Processing and Computer Vision
Methodology
Pattern Recognition
Pattern Recognition and Graphics
Reconfiguration
Signal processing
Signal,Image and Speech Processing
Vision
Reconfigurable architecture
Algorithm/architecture co-design
Deinterlacer
ISSN:1939-8018, 1939-8115
Online-Zugang:Volltext
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Zusammenfassung:This paper presents the algorithm and reconfigurable architecture of motion-adaptive deinterlacer for high-definition video. The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture co-design methodology and Caltrop actor language (CAL) modeling of the dataflow. In the design methodology we employed, the CAL dataflow model is also very helpful in the verification of our deinerlacer. The proposed algorithm and architecture design of deinterlacer is more cost-efficient than two recently proposed works in terms of algorithmic performance and silicon area of VLSI implementation. Moreover, data path reconfiguration efficiently enables various interpolation schemes using less computational resource of hardware than non-reconfigurable architecture.
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ISSN:1939-8018
1939-8115
DOI:10.1007/s11265-009-0388-6