FPGA implementation of HOOFR bucketing extractor-based real-time embedded SLAM applications

Feature extraction is an important vision task in many applications like simultaneous localization and mapping (SLAM). In the recent computing systems, FPGA-based acceleration have presented a strong competition to GPU-based acceleration due to its high computation capabilities and lower energy cons...

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Vydáno v:Journal of real-time image processing Ročník 18; číslo 3; s. 525 - 538
Hlavní autoři: Nguyen, Dai Duong, El Ouardi, Abdelhafid, Rodriguez, Sergio, Bouaziz, Samir
Médium: Journal Article
Jazyk:angličtina
Vydáno: Berlin/Heidelberg Springer Berlin Heidelberg 01.06.2021
Springer Nature B.V
Springer Verlag
Témata:
Algorithms
Computation
Computer Graphics
Computer Science
Design
Designers
Eigenvalues
Energy consumption
Feature extraction
Field programmable gate arrays
High level synthesis
Image Processing and Computer Vision
Memory
Multimedia Information Systems
Neural networks
Original Research Paper
Pattern Recognition
Pixels
Robotics
Signal,Image and Speech Processing
Simultaneous localization and mapping
System on chip
FPGA implementation
Embedded systems
Features extraction
Parallel image processing
ISSN:1861-8200, 1861-8219
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Popis
Shrnutí:Feature extraction is an important vision task in many applications like simultaneous localization and mapping (SLAM). In the recent computing systems, FPGA-based acceleration have presented a strong competition to GPU-based acceleration due to its high computation capabilities and lower energy consumption. In this paper, we present a high-level synthesis implementation on a SoC-FPGA of a feature extraction algorithm dedicated for SLAM applications. We choose HOOFR extraction algorithm which provides a robust performance but requires a significant computation on embedded CPU. Our system is dedicated for SLAM applications so that we also integrated bucketing detection method in order to have a homogeneous distribution of keypoints in the image. Moreover, instead of optimizing performance by simplifying the original algorithm as in many other researches, we respected the complexity of HOOFR extractor and have parallelized the processing operations. The design has been validated on an Intel Arria 10 SoC-FPGA with a throughput of 54 fps at 1226 × 370 pixels (handling 1750 features) or 14 fps at 1920 × 1080 pixels (handling 6929 features).
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ISSN:1861-8200
1861-8219
DOI:10.1007/s11554-020-00986-9