Finite memory test response compactors for embedded test applications

This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100/spl times/, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling...

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Vydané v:IEEE transactions on computer-aided design of integrated circuits and systems Ročník 24; číslo 4; s. 622 - 634
Hlavní autori: Rajski, J., Tyszer, J., Chen Wang, Reddy, S.M.
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.04.2005
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Associate members
Automatic test pattern generation
Built-in self-test
Carbon capture and storage
Circuit testing
Compaction
Convolutional compactors (CCs)
Design for testability
design for testability (DFT)
embedded test
Registers
Semiconductor device testing
spatial compactors
test response compaction
time compactors
Time factors
unknown states
ISSN:0278-0070, 1937-4151
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Shrnutí:This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100/spl times/, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. The CCs can also be used to significantly enhance conventional multiple input signature registers. Experimental results presented in the paper demonstrate the efficiency of convolutional compaction for several industrial circuits.
Bibliografia:ObjectType-Article-2
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2005.844111