Software-Assisted Event Builder for Belle II Experiment

In this article, we present the design of the hybrid event builder algorithm for Belle II DAQ. The event builder is implemented in PCIe40 field-programmable gate array (FPGA) boards and reads up to 48 127 MB/s channels per board. The first version of the event builder implemented the algorithm entir...

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Bibliographic Details

Published in:	IEEE transactions on nuclear science Vol. 72; no. 3; pp. 287 - 294
Main Authors:	Levit, D., Bessner, M., Biswas, D., Charlet, D., Higuchi, T., Itoh, R., Jules, E., Kapusta, P., Kunigo, T., Lai, Y.-T., Lau, T. S., Nakao, M., Nishimura, K., Park, S.-H., Plaige, E., Purwar, H., Robbe, P., Suzuki, S. Y., Taurigna, M., Varner, G., Yamada, S., Zhou, Q.-D.
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.03.2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithms Data acquisition data acquisition systems Data processing Detectors Field programmable gate arrays field-programmable gate arrays (FPGAs) Layout Multiplexing readout systems real-time software systems Software
ISSN:	0018-9499, 1558-1578
Online Access:	Get full text
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