Sakemi, Y., Morino, K., Morie, T., & Aihara, K. (2023). A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design. IEEE transaction on neural networks and learning systems, 34(1), 394-408. https://doi.org/10.1109/TNNLS.2021.3095068
Citácia podle Chicago (17th ed.)Sakemi, Yusuke, Kai Morino, Takashi Morie, a Kazuyuki Aihara. "A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design." IEEE Transaction on Neural Networks and Learning Systems 34, no. 1 (2023): 394-408. https://doi.org/10.1109/TNNLS.2021.3095068.
Citácia podľa MLA (8th ed.)Sakemi, Yusuke, et al. "A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design." IEEE Transaction on Neural Networks and Learning Systems, vol. 34, no. 1, 2023, pp. 394-408, https://doi.org/10.1109/TNNLS.2021.3095068.