A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms but also energy-efficient computational models when implemented in very-large-scale integration (...

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Veröffentlicht in:IEEE transaction on neural networks and learning systems Jg. 34; H. 1; S. 394 - 408
Hauptverfasser: Sakemi, Yusuke, Morino, Kai, Morie, Takashi, Aihara, Kazuyuki
Format: Journal Article
Sprache:Englisch
Veröffentlicht: United States IEEE 01.01.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithms
Coding
Computational neuroscience
Edge computing
Encoding
Energy efficiency
Firing pattern
Information processing
Integrated circuits
Large scale integration
Learning
Machine learning
Manufacturing
Manufacturing industry
Mathematical models
Microprocessors
Multilayers
Neural coding
Neural networks
Neurons
Nonhomogeneous media
Performance enhancement
Recognition
Robustness (mathematics)
Spiking
spiking neural network (SNN)
Supervised learning
Task analysis
temporal coding
Temporal variations
Timing
Very large scale integration
very-large-scale integration (VLSI)
ISSN:2162-237X, 2162-2388, 2162-2388
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Zusammenfassung:Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms but also energy-efficient computational models when implemented in very-large-scale integration (VLSI) circuits. In this article, we propose a novel supervised learning algorithm for SNNs based on temporal coding. A spiking neuron in this algorithm is designed to facilitate analog VLSI implementations with analog resistive memory, by which ultrahigh energy efficiency can be achieved. We also propose several techniques to improve the performance on recognition tasks and show that the classification accuracy of the proposed algorithm is as high as that of the state-of-the-art temporal coding SNN algorithms on the MNIST and Fashion-MNIST datasets. Finally, we discuss the robustness of the proposed SNNs against variations that arise from the device manufacturing process and are unavoidable in analog VLSI implementation. We also propose a technique to suppress the effects of variations in the manufacturing process on the recognition performance.
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ISSN:2162-237X
2162-2388
2162-2388
DOI:10.1109/TNNLS.2021.3095068