A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder

In this paper, an efficient algorithm is proposed to improve the decoding efficiency of the context-based adaptive variable length coding (CAVLC) procedure. Due to the data dependency among symbols in the decoding flow, the CAVLC decoder requires large computation time, which dominates the overall d...

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Vydáno v:IEEE transactions on multimedia Ročník 10; číslo 1; s. 31 - 42
Hlavní autoři: Lin, Heng-Yao, Lu, Ying-Hong, Liu, Bin-Da, Yang, Jar-Ferr
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York, NY IEEE 01.01.2008
Institute of Electrical and Electronic Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Algorithms
Applied sciences
Architecture
Automatic voltage control
Coding
Computer architecture
Computer science; control theory; systems
Computer systems and distributed systems. User interface
Context-based adaptive variable length coding (CAVLC)
Data flow computing
Decoders
Decoding
Energy consumption
Exact sciences and technology
Format
H.264/AVC
Hardware
Pipelines
Power consumption
Software
Studies
Symbols
System performance
Table lookup
variable length coding
Very large scale integration
Performance evaluation
Multimedia
Energy consumption
VLSI circuit
Adaptive detection
Data dependency
Pipeline processor
Critical speed
Decoding circuit
Decoding
Low power
Context aware
Buffer system
Real time
H.264/AVC
Adaptive coding
Context-based adaptive variable length coding iCAVLC
Critical path
variable length coding
Variable length code
ISSN:1520-9210, 1941-0077
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Shrnutí:In this paper, an efficient algorithm is proposed to improve the decoding efficiency of the context-based adaptive variable length coding (CAVLC) procedure. Due to the data dependency among symbols in the decoding flow, the CAVLC decoder requires large computation time, which dominates the overall decoder system performance. To expedite its decoding speed, the critical path in the CAVLC decoder is first analyzed and then reduced by forwarding the adaptive detection for succeeding symbols. With a shortened critical path, the CAVLC architecture is further divided into two segments, which can be easily implemented by a pipeline structure. Consequently, the overall performance is effectively improved. In the hardware implementation, a low power combined LUT and single output buffer have been adopted to reduce the area as well as power consumption without affecting the decoding performance. Experimental results show that the proposed architecture surpassing other recent designs can approximately reduce power consumption by 40% and achieve three times decoding speed in comparison to the original decoding procedure suggested in the H.264 standard. The maximum frequency can be larger than 210 MHz, which can easily support the real-time requirement for resolutions higher than the HD1080 format.
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ISSN:1520-9210
1941-0077
DOI:10.1109/TMM.2007.911299