MacroTrend: A Write-Efficient Cache Algorithm for NVM-Based Read Cache

The future storage systems are expected to contain a wide variety of storage media and layers due to the rapid development of NVM (non-volatile memory) techniques. For NVM-based read caches, many kinds of NVM devices cannot stand frequent data updates due to limited write endurance or high energy co...

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Bibliographic Details
Published in:Journal of computer science and technology Vol. 37; no. 1; pp. 207 - 230
Main Authors: Bao, Ning, Chai, Yun-Peng, Qin, Xiao, Wang, Chuan-Wen
Format: Journal Article
Language:English
Published: Singapore Springer Singapore 01.02.2022
Springer
Springer Nature B.V
Key Laboratory of Data Engineering and Knowledge Engineering,Ministry of Education,Beijing 100872,China
School of Information,Renmin University of China,Beijing 100872,China%Samuel Ginn College of Engineering,Auburn University,Alabama 36830,U.S.A
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ISSN:1000-9000, 1860-4749
Online Access:Get full text
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Summary:The future storage systems are expected to contain a wide variety of storage media and layers due to the rapid development of NVM (non-volatile memory) techniques. For NVM-based read caches, many kinds of NVM devices cannot stand frequent data updates due to limited write endurance or high energy consumption of writing. However, traditional cache algorithms have to update cached blocks frequently because it is difficult for them to predict long-term popularity according to such limited information about data blocks, such as only a single value or a queue that reflects frequency or recency. In this paper, we propose a new MacroTrend (macroscopic trend) prediction method to discover long-term hot blocks through blocks’ macro trends illustrated by their access count histograms. And then a new cache replacement algorithm is designed based on the MacroTrend prediction to greatly reduce the write amount while improving the hit ratio. We conduct extensive experiments driven by a series of real-world traces and find that compared with LRU, MacroTrend can reduce the write amounts of NVM cache devices significantly with similar hit ratios, leading to longer NVM lifetime or less energy consumption.
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ISSN:1000-9000
1860-4749
DOI:10.1007/s11390-021-0178-6