Near-lossless energy-efficient image compression algorithm for wireless capsule endoscopy

•Proposed compressor operates directly on CFA images.•It optimally combines transform-based coding with predictive coding.•Outperforms more complex coding schemes based on JPEG-LS.•Offers excellent energy efficiency: 44μJ per a single 512×512 image frame.•The silicon area of the core is 0.96×0.54mm...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:Biomedical signal processing and control Ročník 38; s. 1 - 8
Hlavní autoři: Turcza, Paweł, Duplaga, Mariusz
Médium: Journal Article
Jazyk:angličtina
Vydáno: Elsevier Ltd 01.09.2017
Témata:
Capsule endoscopy
Image compression
Low power design
VLSI implementation
Image compression
Low power design
VLSI implementation
Capsule endoscopy
ISSN:1746-8094, 1746-8108
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:•Proposed compressor operates directly on CFA images.•It optimally combines transform-based coding with predictive coding.•Outperforms more complex coding schemes based on JPEG-LS.•Offers excellent energy efficiency: 44μJ per a single 512×512 image frame.•The silicon area of the core is 0.96×0.54mm in 180nm CMOS. New near-lossless algorithm for energy efficient image compression in wireless capsule endoscopy (WCE) is proposed. The designed compressor operates directly on data from CMOS image sensor with the Bayer Color Filter Array (CFA). By optimal combining transform-based coding with predictive coding, the proposed compressor achieves higher average image quality and lower bit rate as compared to significantly more complex JPEG-LS based coding schemes. For typical WCE images, the average compression ratio is 3.9, while the PSNR is 46.5dB, which means that very high image quality is achieved. The designed image compressor together with 1KB FIFO (first-in, first-out) stream buffer and a data serializer was implemented in Verilog and synthesised with the UMC 180nm CMOS process as an intellectual property (IP) core. Integrated FIFO and data serializer facilitate low-cost interface to an RF (radio frequency) transmitter. The silicon area of the core is only 0.96×0.54mm. The IP core, operating at clock frequency as low as 5.25MHz, is able to process 20fps (frames per second). It consumes only about 44μJ per a single 512×512 image frame. As such it is very suitable for integration with RF transmitter to form a compact, ultra low-power image processing system for WCE application.
ISSN:1746-8094
1746-8108
DOI:10.1016/j.bspc.2017.04.006