Optimizing hardware function evaluation

We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping, and optimization metrics, such as area, throughput, and latency. Function evaluation f(x...

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Veröffentlicht in:IEEE transactions on computers Jg. 54; H. 12; S. 1520 - 1531
Hauptverfasser: Lee, D.-U., Gaffar, A.A., Mencer, O., Luk, W.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.12.2005
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Application specific integrated circuits
Automated
Circuit optimization
Design engineering
elementary function approximation
gate arrays
Hardware
Index Terms- Computer arithmetic
Logic design
Mathematical analysis
Mathematical models
Matlab
minimax approximation and algorithms
Optimization
Optimization techniques
Programmable logic arrays
Reduction
Studies
ISSN:0018-9340, 1557-9956
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Zusammenfassung:We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping, and optimization metrics, such as area, throughput, and latency. Function evaluation f(x) typically consists of range reduction and the actual evaluation on a small convenient interval such as [0, /spl pi//2) for sin(x). We investigate the impact of hardware function evaluation with range reduction for a given range and precision of x and f(x) on area and speed. An automated bit-width optimization technique for minimizing the sizes of the operators in the data paths is also proposed. We explore a vast design space for fixed-point sin(x), log(x), and /spl radic/x accurate to one unit in the last place using MATLAB and ASC, a stream compiler for field-programmable gate arrays (FPGAs). In this study, we implement over 2,000 placed-and-routed FPGA designs, resulting in over 100 million application-specific integrated circuit (ASIC) equivalent gates. We provide optimal function evaluation results for range and precision combinations between 8 and 48 bits.
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ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2005.201