An events based algorithm for distributing concurrent tasks on multi-core architectures

In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application to a wide range of numerical simulation problems. Such problems involve time stepping or iteration algorithms where sync...

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Vydané v:Computer physics communications Ročník 181; číslo 2; s. 341 - 354
Hlavní autori: Holmes, David W., Williams, John R., Tilke, Peter
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Elsevier B.V 01.02.2010
Predmet:
H-Dispatch
Multi-core
Numerical simulation
Port based programming
95.75.Pq
07.05.Tp
Multi-core
89.20.Ff
Numerical simulation
Port based programming
H-Dispatch
ISSN:0010-4655, 1879-2944
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Popis
Shrnutí:In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application to a wide range of numerical simulation problems. Such problems involve time stepping or iteration algorithms where synchronization of multiple threads of execution is required. It is shown that traditional approaches to parallelism including message passing and scatter-gather can be improved upon in terms of speed-up and memory management. Using spatial decomposition to create orthogonal computational tasks, a new task management algorithm called H-Dispatch is developed. This algorithm makes efficient use of memory resources by limiting the need for garbage collection and takes optimal advantage of multiple cores by employing a “hungry” pull strategy. The technique is demonstrated on a simple finite difference solver and results are compared to traditional MPI and scatter-gather approaches. The H-Dispatch approach achieves near linear speed-up with results for efficiency of 85% on a 24-core machine. It is noted that the H-Dispatch algorithm is quite general and can be applied to a wide class of computational tasks on heterogeneous architectures involving multi-core and GPGPU hardware.
ISSN:0010-4655
1879-2944
DOI:10.1016/j.cpc.2009.10.009