SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation

The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience e...

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Vydáno v:IEEE journal of solid-state circuits Ročník 48; číslo 8; s. 1943 - 1953
Hlavní autoři: Painkras, Eustace, Plana, Luis A., Garside, Jim, Temple, Steve, Galluppi, Francesco, Patterson, Cameron, Lester, David R., Brown, Andrew D., Furber, Steve B.
Médium: Journal Article Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY IEEE 01.08.2013
Institute of Electrical and Electronics Engineers
Témata:
ISSN:0018-9200, 1558-173X
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Abstract The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm 2 die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements.
AbstractList The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm 2 die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements.
Author Brown, Andrew D.
Temple, Steve
Patterson, Cameron
Garside, Jim
Galluppi, Francesco
Furber, Steve B.
Lester, David R.
Painkras, Eustace
Plana, Luis A.
Author_xml – sequence: 1
  givenname: Eustace
  surname: Painkras
  fullname: Painkras, Eustace
  organization: Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
– sequence: 2
  givenname: Luis A.
  surname: Plana
  fullname: Plana, Luis A.
  email: luis.plana@manchester.ac.uk
  organization: Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
– sequence: 3
  givenname: Jim
  surname: Garside
  fullname: Garside, Jim
  organization: Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
– sequence: 4
  givenname: Steve
  surname: Temple
  fullname: Temple, Steve
  organization: Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
– sequence: 5
  givenname: Francesco
  surname: Galluppi
  fullname: Galluppi, Francesco
  organization: Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
– sequence: 6
  givenname: Cameron
  surname: Patterson
  fullname: Patterson, Cameron
  organization: Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
– sequence: 7
  givenname: David R.
  surname: Lester
  fullname: Lester, David R.
  organization: Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
– sequence: 8
  givenname: Andrew D.
  surname: Brown
  fullname: Brown, Andrew D.
  organization: Electron. & Electr. Eng., Univ. of Southampton, Southampton, UK
– sequence: 9
  givenname: Steve B.
  surname: Furber
  fullname: Furber, Steve B.
  organization: Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
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Issue 8
Keywords Spiking neuron
Processor
Asynchronous interconnect
neuromorphic hardware
Modeling
Implementation
Multiprocessor
Microelectronic fabrication
Parallel system
globally asynchronous locally synchronous (GALS)
energy efficiency
Parallel processing
chip multiprocessor
Chemical mechanical polishing
Computer design
spiking neural networks (SNNs)
Large scale system
Globally asynchronous locally synchronous
Packet switching
network-on-chip
System design
System on a chip
Parallel architectures
Parallel computer
Neural network
Synapse
real-time simulation
Integrated circuit
Computer system
Simulator
Asynchronous transmission
Language English
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PublicationDate 2013-08-01
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PublicationTitle IEEE journal of solid-state circuits
PublicationTitleAbbrev JSSC
PublicationYear 2013
Publisher IEEE
Institute of Electrical and Electronics Engineers
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Snippet The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural...
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SubjectTerms Applied sciences
Asynchronous interconnect
Biological system modeling
Brain modeling
chip multiprocessor
Computational modeling
Computer systems
Electric, optical and optoelectronic circuits
Electronics
energy efficiency
Exact sciences and technology
globally asynchronous locally synchronous (GALS)
Hardware
Integrated circuits
Integrated circuits by function (including memories and processors)
network-on-chip
Neural networks
neuromorphic hardware
Neurons
real-time simulation
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
spiking neural networks (SNNs)
System-on-chip
Transistors
Title SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation
URI https://ieeexplore.ieee.org/document/6515159
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