Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware sy...

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Published in:	Microprocessors and microsystems Vol. 80; p. 103514
Main Authors:	Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra
Format:	Journal Article
Language:	English
Published:	Kidlington Elsevier B.V 01.02.2021 Elsevier BV
Subjects:	Algorithms Computer vision Corner detection Design Field programmable gate arrays Field-programmable gate array Gate counting Hardware description language Hardware description languages Harris corner detection High level synthesis High speed Image processing MATLAB HDL coder Real time Register transfer language Video data Vivado Hardware description language High-Level Synthesis Harris corner detection Vivado Field-programmable gate array MATLAB HDL coder Register transfer language
ISSN:	0141-9331, 1872-9436
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Abstract	Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using MATLAB HDL coder for HLS. The generated hardware description language (HDL) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area(smaller gate count on target FPGA) and speed for the same target board.
AbstractList	Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using MATLAB HDL coder for HLS. The generated hardware description language (HDL) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area(smaller gate count on target FPGA) and speed for the same target board.
ArticleNumber	103514
Author	Shekhar, Chandra Sikka, Prateek Asati, Abhijit R.
Author_xml	– sequence: 1 givenname: Prateek surname: Sikka fullname: Sikka, Prateek email: prateeksikka@gmail.com – sequence: 2 givenname: Abhijit R. surname: Asati fullname: Asati, Abhijit R. email: abhijit_asati@pilani.bits-pilani.ac.in – sequence: 3 givenname: Chandra surname: Shekhar fullname: Shekhar, Chandra email: chandra.shekhar@pilani.bits-pilani.ac.in
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Keywords	Hardware description language High-Level Synthesis Harris corner detection Vivado Field-programmable gate array MATLAB HDL coder Register transfer language
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References	Vourvoulakis, Kalomiros, Lygouras (bib0008) 2016; 40 Schulz, Bombardelli, Todt (bib0001) 2016; 619 Kucukcakar, Chen, Gong, Philipsen, Tkacik (bib0014) 1998; 15 Lippens, van Meerbergen, van der Werf, Verhaegh, McSweeney, Huisken, McArdle (bib0015) 1991 Biesenack, Koster, Langmaier, Ledeux, Marz, Payer, Pilsl, Rumler, Soukup, Wehn, Duzy (bib0016) 1993; 1 Catapult H.L.S., (2019) Liu (bib0004) 2017 Komorkiewicz, Kryjak, Chuchacz-Kowalczyk, Skruch, Gorgoń (bib0003) 2015 (accessed 12 Sep, 2019). Xu, Yunshan (bib0005) 2017 Ahmed, Sidek (bib0009) 2017; 49 MathWorks HDL coder. (2019) . Cong, Liu, Neuendorffer, Noguera, Vissers, Zhang (bib0012) 2011; 30 Bergamaschi, O'Connor, Stok, Moricz, Prakash, Kuehlmann, Rao (bib0013) 1995; 39 Chao, Kin (bib0006) 2015 Xilinx, (2018) Vivado design suite: high-level synthesis. (accessed 14 Aug, 2019). Cabani (bib0002) 2006 Lee, Wang, Chen, Chuang, Chang, Chou (bib0007) 2014; 2014 Stratus H.L.S., (2019) Knapp (bib0017) 1996 MathWorks HDL Verifier, (2019) Biesenack (10.1016/j.micpro.2020.103514_bib0016) 1993; 1 Xu (10.1016/j.micpro.2020.103514_bib0005) 2017 10.1016/j.micpro.2020.103514_bib0011 Lippens (10.1016/j.micpro.2020.103514_bib0015) 1991 Knapp (10.1016/j.micpro.2020.103514_bib0017) 1996 10.1016/j.micpro.2020.103514_bib0020 10.1016/j.micpro.2020.103514_bib0010 Ahmed (10.1016/j.micpro.2020.103514_bib0009) 2017; 49 Bergamaschi (10.1016/j.micpro.2020.103514_bib0013) 1995; 39 Kucukcakar (10.1016/j.micpro.2020.103514_bib0014) 1998; 15 Chao (10.1016/j.micpro.2020.103514_bib0006) 2015 Cong (10.1016/j.micpro.2020.103514_bib0012) 2011; 30 Liu (10.1016/j.micpro.2020.103514_bib0004) 2017 Lee (10.1016/j.micpro.2020.103514_bib0007) 2014; 2014 Schulz (10.1016/j.micpro.2020.103514_bib0001) 2016; 619 Vourvoulakis (10.1016/j.micpro.2020.103514_bib0008) 2016; 40 10.1016/j.micpro.2020.103514_bib0019 Cabani (10.1016/j.micpro.2020.103514_bib0002) 2006 Komorkiewicz (10.1016/j.micpro.2020.103514_bib0003) 2015 10.1016/j.micpro.2020.103514_bib0018
References_xml	– reference: (accessed 12 Sep, 2019). – reference: , (accessed 14 Aug, 2019). – year: 2017 ident: bib0005 article-title: Implementation of Harris corner matching based on FPGA publication-title: 2017 6th International Conference on Energy and Environmental Protection (ICEEP 2017). – reference: MathWorks HDL coder. (2019) – start-page: 339 year: 2017 end-page: 343 ident: bib0004 article-title: Real time implementation of Harris corner detection system based on FPGA publication-title: 2017 IEEE International Conference on Real time Computing and Robotics (RCAR) – reference: Catapult H.L.S., (2019) – reference: Xilinx, (2018) Vivado design suite: high-level synthesis. – volume: 619 year: 2016 ident: bib0001 article-title: A Harris corner detector implementation in SoC-FPGA for visual SLAM publication-title: Robotics. SBR 2016, LARS 2016. Communications in Computer and Information Science – volume: 40 start-page: 53 year: 2016 end-page: 73 ident: bib0008 article-title: Fully pipelined FPGA-based architecture for real-time SIFT extraction publication-title: Microprocess. Microsyst. – volume: 39 start-page: 131 year: 1995 end-page: 148 ident: bib0013 article-title: High-level synthesis in an industrial environment publication-title: IBM J. Res. Develop. – volume: 2014 year: 2014 ident: bib0007 article-title: A modified Harris corner detection for breast IR image publication-title: Math. Probl. Eng. – volume: 1 start-page: 244 year: 1993 end-page: 253 ident: bib0016 article-title: The Siemens high-level synthesis system CALLAS publication-title: IEEE Trans. Very Large Scale Integr. Syst. – year: 1996 ident: bib0017 article-title: Behavioral Synthesis: digital System Design Using the Synopsys Behavioral Compiler – reference: . – volume: 30 start-page: 473 year: 2011 end-page: 491 ident: bib0012 article-title: High-level synthesis for FPGAs: from prototyping to deployment publication-title: IEEE T. Comput. Aid. D – start-page: 5 year: 2006 end-page: 13 ident: bib0002 article-title: Implementation of an Affine-Invariant Feature Detector in Field-Programmable Gate Arrays – volume: 15 start-page: 22 year: 1998 end-page: 33 ident: bib0014 article-title: Matisse: an architectural design tool for commodity ICs publication-title: IEEE DesTest Comput. – volume: 49 start-page: 164 year: 2017 end-page: 178 ident: bib0009 article-title: An energy-aware self-adaptive System-on-Chip architecture for real-time Harris corner detection with multi-resolution support publication-title: Microprocess. Microsyst. – start-page: 1 year: 2015 end-page: 7 ident: bib0003 article-title: FPGA based system for real time structure from motion computation publication-title: 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) – start-page: 436 year: 1991 end-page: 441 ident: bib0015 article-title: PHIDEO: a silicon compiler for high speed algorithms publication-title: Proceedings of the European Conference on Design Automation – reference: Stratus H.L.S., (2019) – year: 2015 ident: bib0006 article-title: An efficient FPGA implementation of the Harris corner feature detector publication-title: 2015 14th IAPR International Conference on Machine Vision Applications (MVA). – reference: MathWorks HDL Verifier, (2019) – volume: 30 start-page: 473 year: 2011 ident: 10.1016/j.micpro.2020.103514_bib0012 article-title: High-level synthesis for FPGAs: from prototyping to deployment publication-title: IEEE T. Comput. Aid. D doi: 10.1109/TCAD.2011.2110592 – volume: 619 year: 2016 ident: 10.1016/j.micpro.2020.103514_bib0001 article-title: A Harris corner detector implementation in SoC-FPGA for visual SLAM – year: 2015 ident: 10.1016/j.micpro.2020.103514_bib0006 article-title: An efficient FPGA implementation of the Harris corner feature detector – ident: 10.1016/j.micpro.2020.103514_bib0020 – start-page: 5 year: 2006 ident: 10.1016/j.micpro.2020.103514_bib0002 – start-page: 436 year: 1991 ident: 10.1016/j.micpro.2020.103514_bib0015 article-title: PHIDEO: a silicon compiler for high speed algorithms – year: 2017 ident: 10.1016/j.micpro.2020.103514_bib0005 article-title: Implementation of Harris corner matching based on FPGA – ident: 10.1016/j.micpro.2020.103514_bib0018 – start-page: 339 year: 2017 ident: 10.1016/j.micpro.2020.103514_bib0004 article-title: Real time implementation of Harris corner detection system based on FPGA – ident: 10.1016/j.micpro.2020.103514_bib0019 – volume: 40 start-page: 53 year: 2016 ident: 10.1016/j.micpro.2020.103514_bib0008 article-title: Fully pipelined FPGA-based architecture for real-time SIFT extraction publication-title: Microprocess. Microsyst. doi: 10.1016/j.micpro.2015.11.013 – ident: 10.1016/j.micpro.2020.103514_bib0011 – volume: 49 start-page: 164 year: 2017 ident: 10.1016/j.micpro.2020.103514_bib0009 article-title: An energy-aware self-adaptive System-on-Chip architecture for real-time Harris corner detection with multi-resolution support publication-title: Microprocess. Microsyst. doi: 10.1016/j.micpro.2016.11.016 – volume: 39 start-page: 131 year: 1995 ident: 10.1016/j.micpro.2020.103514_bib0013 article-title: High-level synthesis in an industrial environment publication-title: IBM J. Res. Develop. doi: 10.1147/rd.391.0131 – start-page: 1 year: 2015 ident: 10.1016/j.micpro.2020.103514_bib0003 article-title: FPGA based system for real time structure from motion computation – ident: 10.1016/j.micpro.2020.103514_bib0010 – volume: 2014 year: 2014 ident: 10.1016/j.micpro.2020.103514_bib0007 article-title: A modified Harris corner detection for breast IR image publication-title: Math. Probl. Eng. doi: 10.1155/2014/902659 – year: 1996 ident: 10.1016/j.micpro.2020.103514_bib0017 – volume: 15 start-page: 22 year: 1998 ident: 10.1016/j.micpro.2020.103514_bib0014 article-title: Matisse: an architectural design tool for commodity ICs publication-title: IEEE DesTest Comput. doi: 10.1109/54.679205 – volume: 1 start-page: 244 year: 1993 ident: 10.1016/j.micpro.2020.103514_bib0016 article-title: The Siemens high-level synthesis system CALLAS publication-title: IEEE Trans. Very Large Scale Integr. Syst. doi: 10.1109/92.238438
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Snippet	Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most...
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SubjectTerms	Algorithms Computer vision Corner detection Design Field programmable gate arrays Field-programmable gate array Gate counting Hardware description language Hardware description languages Harris corner detection High level synthesis High speed Image processing MATLAB HDL coder Real time Register transfer language Video data Vivado
Title	Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm
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