Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware sy...

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Bibliographic Details
Published in:Microprocessors and microsystems Vol. 80; p. 103514
Main Authors: Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra
Format: Journal Article
Language:English
Published: Kidlington Elsevier B.V 01.02.2021
Elsevier BV
Subjects:
Algorithms
Computer vision
Corner detection
Design
Field programmable gate arrays
Field-programmable gate array
Gate counting
Hardware description language
Hardware description languages
Harris corner detection
High level synthesis
High speed
Image processing
MATLAB HDL coder
Real time
Register transfer language
Video data
Vivado
Hardware description language
High-Level Synthesis
Harris corner detection
Vivado
Field-programmable gate array
MATLAB HDL coder
Register transfer language
ISSN:0141-9331, 1872-9436
Online Access:Get full text
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Summary:Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using MATLAB HDL coder for HLS. The generated hardware description language (HDL) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area(smaller gate count on target FPGA) and speed for the same target board.
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ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2020.103514