The SegBus platform – architecture and communication mechanisms

In this study, we introduce the SegBus architecture, a synchronous segmented bus platform for systems on chip. We present the envisioned structure in detail, and also address aspects of communication on the platform. The motivation behind SegBus is the search for performance improvements, in several...

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Veröffentlicht in:	Journal of systems architecture Jg. 53; H. 4; S. 151 - 169
1. Verfasser:	Seceleanu, Tiberiu
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Amsterdam Elsevier B.V 01.04.2007 Elsevier Sequoia S.A
Schlagworte:	Computer architecture Computer platforms Field programmable gate arrays FPGA On-chip communication Platform design Segmented bus Studies Platform design Segmented bus On-chip communication FPGA
ISSN:	1383-7621, 1873-6165
Online-Zugang:	Volltext
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