A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing

The massively parallel computing systems composed of many processors are connected on chips, which will become more and more complex and unreliable. This paper presents an error-tolerant design based on the autonomous error-tolerant (AET) architecture that aims to have a self-repairing capability. A...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems Jg. 26; H. 10; S. 2143 - 2154
Hauptverfasser:	Liu, Lizheng, Jin, Yi, Liu, Yi, Ma, Ning, Huan, Yuxiang, Zou, Zhuo, Zheng, Lirong
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.10.2018 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Circuit faults Computation Computer architecture Embedded systems Error analysis Error detection Error tolerant Maintenance Microprocessors nanosystem Parallel processing Power consumption Processors Program processors Redundancy self-reparation sensing Sensors
ISSN:	1063-8210, 1557-9999, 1557-9999
Online-Zugang:	Volltext
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