A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing

The massively parallel computing systems composed of many processors are connected on chips, which will become more and more complex and unreliable. This paper presents an error-tolerant design based on the autonomous error-tolerant (AET) architecture that aims to have a self-repairing capability. A...

Celý popis

Uložené v:

Podrobná bibliografia
Vydané v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 26; číslo 10; s. 2143 - 2154
Hlavní autori:	Liu, Lizheng, Jin, Yi, Liu, Yi, Ma, Ning, Huan, Yuxiang, Zou, Zhuo, Zheng, Lirong
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.10.2018 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Circuit faults Computation Computer architecture Embedded systems Error analysis Error detection Error tolerant Maintenance Microprocessors nanosystem Parallel processing Power consumption Processors Program processors Redundancy self-reparation sensing Sensors
ISSN:	1063-8210, 1557-9999, 1557-9999
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!

Buďte prvý, kto okomentuje tento záznam!