Fault-tolerant programmable logic array for nanoelectronics

SUMMARY This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure syste...

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Bibliographic Details

Published in:	International journal of circuit theory and applications Vol. 40; no. 12; pp. 1233 - 1247
Main Authors:	Flak, Jacek, Laiho, Mika
Format:	Journal Article
Language:	English
Published:	Chichester, UK John Wiley & Sons, Ltd 01.12.2012 Wiley Subscription Services, Inc
Subjects:	fault tolerance hybrid circuits nanoelectronics programmable logic array single-electron devices
ISSN:	0098-9886, 1097-007X
Online Access:	Get full text
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