Fault-tolerant programmable logic array for nanoelectronics

SUMMARY This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure syste...

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Veröffentlicht in:International journal of circuit theory and applications Jg. 40; H. 12; S. 1233 - 1247
Hauptverfasser: Flak, Jacek, Laiho, Mika
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Chichester, UK John Wiley & Sons, Ltd 01.12.2012
Wiley Subscription Services, Inc
Schlagworte:
fault tolerance
hybrid circuits
nanoelectronics
programmable logic array
single-electron devices
ISSN:0098-9886, 1097-007X
Online-Zugang:Volltext
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Zusammenfassung:SUMMARY This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single‐electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies. Copyright © 2012 John Wiley & Sons, Ltd. An architecture for nanoelectronic logic system is presented, in which regular array of nanoscale logic gates is accompanied by CMOS control circuitry. Binary programmable interconnections provide means of computing different logic operations. They also allow for setting the redundancy level via the number of columns clustered to compute a certain function. The embedded fault‐tolerance scheme can effectively mitigate permanent as well as transient faults. The proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies.
Bibliographie:istex:4EAD3A4C0ADA2266229E0EF18C10112CA94F71B1
ark:/67375/WNG-H8BWC601-8
ArticleID:CTA1795
ObjectType-Article-1
SourceType-Scholarly Journals-1
content type line 14
ISSN:0098-9886
1097-007X
DOI:10.1002/cta.1795