Ternary encoder and decoder designs in RRAM and CNTFET technologies
•Design of low-power technique for unbalanced ternary logic system.•Ternary encoder and decoder designs for low-power applications.•RRAM idea to implement the ternary logic.•Ternary logic is generated using CNTFET nanotechnology.•Outlined the ternary approach for logic implementation. A possible way...
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01.03.2024
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| Abstract | •Design of low-power technique for unbalanced ternary logic system.•Ternary encoder and decoder designs for low-power applications.•RRAM idea to implement the ternary logic.•Ternary logic is generated using CNTFET nanotechnology.•Outlined the ternary approach for logic implementation.
A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied. |
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| AbstractList | A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied. •Design of low-power technique for unbalanced ternary logic system.•Ternary encoder and decoder designs for low-power applications.•RRAM idea to implement the ternary logic.•Ternary logic is generated using CNTFET nanotechnology.•Outlined the ternary approach for logic implementation. A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied. |
| ArticleNumber | 100397 |
| Author | Sharma, Vijay Kumar Haq, Shams Ul |
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| Cites_doi | 10.1088/2631-8695/ac0fc6 10.1109/TNANO.2009.2036845 10.1049/iet-cds.2010.0340 10.1088/0268-1242/31/11/113001 10.3390/electronics9040542 10.1109/JSSC.1984.1052216 10.1002/cta.3667 10.1109/ACCESS.2019.2928251 10.1109/TED.2016.2545412 10.1049/iet-cdt.2013.0023 10.1007/s13369-023-07618-x 10.1080/00207217.2021.1908620 10.4236/cs.2016.74036 10.1109/TCSI.2021.3121437 10.1186/s11671-020-03299-9 10.1109/ACCESS.2020.2997809 10.1016/j.mejo.2017.02.018 10.1166/jctn.2010.1517 10.3390/electronics9010200 10.1109/TNANO.2018.2800015 10.1155/2016/6303725 10.3390/nano10081437 10.1016/j.aeue.2023.154601 10.1063/1.4954974 10.1149/2162-8777/acc137 10.1007/s13369-023-08053-8 10.1116/1.4973372 10.1039/C5RA22728C 10.1080/00207210701295061 10.1039/C8RA03181A 10.1002/pssa.201532813 10.1109/JEDS.2018.2805285 |
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