A parallel Viterbi decoding algorithm

In this paper we express the Viterbi algorithm as a matrix–vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array. We describe the algorith...

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Bibliographic Details
Published in:Concurrency and computation Vol. 13; no. 2; pp. 95 - 102
Main Author: Reeve, J. S.
Format: Journal Article
Language:English
Published: Chichester, UK John Wiley & Sons, Ltd 01.02.2001
Subjects:
BCH codes
trellis decoding
Viterbi decoding
ISSN:1532-0626, 1532-0634
Online Access:Get full text
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Summary:In this paper we express the Viterbi algorithm as a matrix–vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array. We describe the algorithm for Bose–Chaudhuri–Hocquenghem (BCH) codes which have a task graph with its valence restricted to four inputs and four outputs. The method is also applicable to convolution codes, but the complexity of the task graph increases with the number of input bits for these codes. Results for BCH codes are given for two general purpose parallel machines, an IBM SP2 and a Meiko CS2. Copyright © 2001 John Wiley & Sons, Ltd.
Bibliography:ArticleID:CPE539
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content type line 23
ISSN:1532-0626
1532-0634
DOI:10.1002/cpe.539