A parallel Viterbi decoding algorithm

In this paper we express the Viterbi algorithm as a matrix–vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array. We describe the algorith...

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Bibliographic Details
Published in:	Concurrency and computation Vol. 13; no. 2; pp. 95 - 102
Main Author:	Reeve, J. S.
Format:	Journal Article
Language:	English
Published:	Chichester, UK John Wiley & Sons, Ltd 01.02.2001
Subjects:	BCH codes trellis decoding Viterbi decoding
ISSN:	1532-0626, 1532-0634
Online Access:	Get full text
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