Testing Resistive Opens and Bridging Faults Through Pulse Propagation

This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by traditional delay fault testing because the induced delay defects are not large enough to result in timing violations when the test rate is equ...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:IEEE transactions on computer-aided design of integrated circuits and systems Ročník 28; číslo 6; s. 915 - 925
Hlavní autori: Favalli, M., Metra, C.
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.06.2009
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Bridging
Bridging faults
Circuit faults
Circuit testing
Circuits
Clocks
Computer aided design
Degradation
Delay
Design engineering
digital ICs' testing
Electrical fault detection
Fault detection
Faults
Frequency
open faults
Pulse circuits
Studies
test generation
Timing
timing defects
ISSN:0278-0070, 1937-4151
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by traditional delay fault testing because the induced delay defects are not large enough to result in timing violations when the test rate is equal to the nominal operating frequency. In spite of this problem, resistive opens and bridgings should be detected because they may give rise to reliability problems. To detect them, we propose a testing method that is based on the propagation of pulses within the faulty circuit and that exploits the degraded capability of faulty paths to propagate pulses. The effectiveness of our method is analyzed at the transistor level and compared with the use of reduced clock periods to detect the same class of faults. Results show similar performance in the case of resistive opens and better performance in the case of bridgings. Moreover, the proposed approach is not affected by possible problems in the clock distribution.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ObjectType-Article-2
ObjectType-Feature-1
content type line 23
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2009.2017080