FPGA Implementation of the C-Mantec Neural Network Constructive Algorithm

Competitive majority network trained by error correction (C-Mantec), a recently proposed constructive neural network algorithm that generates very compact architectures with good generalization capabilities, is implemented in a field programmable gate array (FPGA). A clear difference with most of th...

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Vydané v:	IEEE transactions on industrial informatics Ročník 10; číslo 2; s. 1154 - 1161
Hlavní autori:	Ortega-Zamorano, Francisco, Jerez, Jose M., Franco, Leonardo
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Piscataway IEEE 01.05.2014 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Algorithms Circuit complexity Construction Construction industry constructive neural networks (CoNN) Field programmable gate arrays Hardware Learning Neural networks Neurons on-chip learning Table lookup Tasks threshold networks Training
ISSN:	1551-3203, 1941-0050
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