FPGA Implementation of the C-Mantec Neural Network Constructive Algorithm

Competitive majority network trained by error correction (C-Mantec), a recently proposed constructive neural network algorithm that generates very compact architectures with good generalization capabilities, is implemented in a field programmable gate array (FPGA). A clear difference with most of th...

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Bibliographic Details
Published in:IEEE transactions on industrial informatics Vol. 10; no. 2; pp. 1154 - 1161
Main Authors: Ortega-Zamorano, Francisco, Jerez, Jose M., Franco, Leonardo
Format: Journal Article
Language:English
Published: Piscataway IEEE 01.05.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN:1551-3203, 1941-0050
Online Access:Get full text
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Summary:Competitive majority network trained by error correction (C-Mantec), a recently proposed constructive neural network algorithm that generates very compact architectures with good generalization capabilities, is implemented in a field programmable gate array (FPGA). A clear difference with most of the existing neural network implementations (most of them based on the use of the backpropagation algorithm) is that the C-Mantec automatically generates an adequate neural architecture while the training of the data is performed. All the steps involved in the implementation, including the on-chip learning phase, are fully described and a deep analysis of the results is carried on using the two sets of benchmark problems. The results show a clear increase in the computation speed in comparison to the standard personal computer (PC)-based implementation, demonstrating the usefulness of the intrinsic parallelism of FPGAs in the neurocomputational tasks and the suitability of the hardware version of the C-Mantec algorithm for its application to real-world problems.
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ISSN:1551-3203
1941-0050
DOI:10.1109/TII.2013.2294137