Direct Neural-Network Hardware-Implementation Algorithm

An algorithm for compact neural-network hardware implementation is presented, which exploits the special properties of the Boolean functions describing the operation of artificial neurons with step activation function. The algorithm contains three steps: artificial-neural-network (ANN) mathematical...

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Veröffentlicht in:IEEE transactions on industrial electronics (1982) Jg. 57; H. 5; S. 1845 - 1848
Hauptverfasser: Dinu, Andrei, Cirstea, Marcian N, Cirstea, Silvia E
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.05.2010
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Activation
Algorithms
Artificial neural networks
Boolean functions
Bridge circuits
Digitization
Field-programmable gate array (FPGA)
Hardware
Hardware design languages
hardware implementation
Integrated circuit packaging
Learning theory
Logic gates
Mathematical analysis
Mathematical model
Mathematical models
Neural networks
Neurons
Software design
Very high speed integrated circuits
ISSN:0278-0046, 1557-9948
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Beschreibung
Zusammenfassung:An algorithm for compact neural-network hardware implementation is presented, which exploits the special properties of the Boolean functions describing the operation of artificial neurons with step activation function. The algorithm contains three steps: artificial-neural-network (ANN) mathematical model digitization, conversion of the digitized model into a logic-gate structure, and hardware optimization by elimination of redundant logic gates. A set of C++ programs automates algorithm implementation, generating an optimized very high speed integrated circuit hardware description language code. This strategy bridges the gap between ANN design software and hardware design packages (Xilinx). Although the method is directly applicable only to neurons with step activation functions, it can be extended to sigmoidal functions.
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ISSN:0278-0046
1557-9948
DOI:10.1109/TIE.2009.2033097