Direct Neural-Network Hardware-Implementation Algorithm

An algorithm for compact neural-network hardware implementation is presented, which exploits the special properties of the Boolean functions describing the operation of artificial neurons with step activation function. The algorithm contains three steps: artificial-neural-network (ANN) mathematical...

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Vydané v:	IEEE transactions on industrial electronics (1982) Ročník 57; číslo 5; s. 1845 - 1848
Hlavní autori:	Dinu, Andrei, Cirstea, Marcian N, Cirstea, Silvia E
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.05.2010 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Activation Algorithms Artificial neural networks Boolean functions Bridge circuits Digitization Field-programmable gate array (FPGA) Hardware Hardware design languages hardware implementation Integrated circuit packaging Learning theory Logic gates Mathematical analysis Mathematical model Mathematical models Neural networks Neurons Software design Very high speed integrated circuits
ISSN:	0278-0046, 1557-9948
On-line prístup:	Získať plný text
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