Efficient VLSI Architecture for Soft-Decision Decoding of Reed-Solomon Codes

Reed-Solomon (RS) codes have very broad applications in digital communication and storage systems. The developed algebraic soft-decision decoding (ASD) algorithms of RS codes can achieve substantial coding gain with polynomial complexity. Among the ASD algorithms with practical multiplicity assignme...

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Veröffentlicht in:IEEE transactions on circuits and systems. I, Regular papers Jg. 55; H. 10; S. 3050 - 3062
Hauptverfasser: Jiangli Zhu, Jiangli Zhu, Xinmiao Zhang, Xinmiao Zhang
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.11.2008
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algebraic soft-decision decoding
Algorithms
Codes
Computer architecture
Decoding
Digital communication
factorization
Galois fields
Interpolation
Lee-O'Sullivan algorithm
Parallel processing
Polynomials
Reed-Solomon codes
Studies
Variable speed drives
Very large scale integration
VLSI architecture
Reed-Solomon codes
Interpolation
Lee-O Sullivan algorithm
VLSI architecture
Algebraic soft-decision decoding
Factorization
ISSN:1549-8328, 1558-0806
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Zusammenfassung:Reed-Solomon (RS) codes have very broad applications in digital communication and storage systems. The developed algebraic soft-decision decoding (ASD) algorithms of RS codes can achieve substantial coding gain with polynomial complexity. Among the ASD algorithms with practical multiplicity assignment schemes, the bit-level generalized minimum distance (BGMD) decoding algorithm can achieve similar or higher coding gain with lower complexity. ASD algorithms consist of two major steps: the interpolation and the factorization. In this paper, novel architectures for both steps are proposed for the BGMD decoder. The interpolation architecture is based on the newly proposed Lee-O'Sullivan (LO) algorithm. By exploiting the characteristics of the LO algorithm and the multiplicity assignment scheme in the BGMD decoder, the proposed interpolation architecture for a (255, 239) RS code can achieve 25% higher efficiency in terms of speed/area ratio than prior efforts. Root computation over finite fields and polynomial updating are the two main steps of the factorization. A low-latency and prediction-free scheme is introduced in this paper for the root computation in the BGMD decoder. In addition, novel coefficient storage schemes and parallel processing architectures are developed to reduce the latency of the polynomial updating. The proposed factorization architecture is 126% more efficient than the previous direct root computation factorization architecture.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.923169