Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform

For the overall performance of systems like microprocessors and digital signal processors (DSPs) platforms, arithmetic units, all must be efficient in terms of speed, power, and area. Multipliers and dividers are inevitable hardware employed in such systems. This paper focuses on Vedic mathematics a...

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Vydané v:	Sadhana (Bangalore) Ročník 46; číslo 2
Hlavní autori:	Biji, Rhea, Savani, Vijay
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New Delhi Springer India 01.06.2021 Springer Nature B.V
Predmet:	Algorithms Arithmetic and logic units CMOS Convolution Digital signal processing Digital signal processors Dividers Dividing (mathematics) Engineering Hardware Mathematical analysis Mathematics Microprocessors Multiplication Multiplication & division Power consumption Vedic mathematics algorithms Nikhilam Sutra Urdhva Tiryagbhyam Digital signal processing Verilog
ISSN:	0256-2499, 0973-7677
On-line prístup:	Získať plný text
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