HDSAP: heterogeneity-aware dynamic scheduling algorithm to improve performance of nanoscale many-core processors for unknown workloads

The performance growth in processors has been continuing toward increasing the number of processing cores on the chip and scaling the feature size of transistors. However, in the nanoera, side effects of the scaling, such as induced heterogeneities in the performance, power, and soft error rate of i...

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Bibliographic Details
Published in:	The Journal of supercomputing Vol. 79; no. 12; pp. 13341 - 13369
Main Authors:	Kia, Keihaneh, Rajabzadeh, Amir
Format:	Journal Article
Language:	English
Published:	New York Springer US 01.08.2023 Springer Nature B.V
Subjects:	Algorithms Communication Compilers Computer Science Constraints Design Heterogeneity Heuristic scheduling Interpreters Manufacturing Mathematical models Microprocessors Performance enhancement Processor Architectures Processors Programming Languages Reliability Response time Scheduling Side effects Simulators Soft errors Transistors Workload Workloads Nanoscale Soft error reliability Manufacturing process variation Power limitation Multi many-core processor Static NUCA architecture
ISSN:	0920-8542, 1573-0484
Online Access:	Get full text
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