HDSAP: heterogeneity-aware dynamic scheduling algorithm to improve performance of nanoscale many-core processors for unknown workloads

The performance growth in processors has been continuing toward increasing the number of processing cores on the chip and scaling the feature size of transistors. However, in the nanoera, side effects of the scaling, such as induced heterogeneities in the performance, power, and soft error rate of i...

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Bibliographic Details
Published in:The Journal of supercomputing Vol. 79; no. 12; pp. 13341 - 13369
Main Authors: Kia, Keihaneh, Rajabzadeh, Amir
Format: Journal Article
Language:English
Published: New York Springer US 01.08.2023
Springer Nature B.V
Subjects:
Algorithms
Communication
Compilers
Computer Science
Constraints
Design
Heterogeneity
Heuristic scheduling
Interpreters
Manufacturing
Mathematical models
Microprocessors
Performance enhancement
Processor Architectures
Processors
Programming Languages
Reliability
Response time
Scheduling
Side effects
Simulators
Soft errors
Transistors
Workload
Workloads
Nanoscale
Soft error reliability
Manufacturing process variation
Power limitation
Multi many-core processor
Static NUCA architecture
ISSN:0920-8542, 1573-0484
Online Access:Get full text
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Summary:The performance growth in processors has been continuing toward increasing the number of processing cores on the chip and scaling the feature size of transistors. However, in the nanoera, side effects of the scaling, such as induced heterogeneities in the performance, power, and soft error rate of identically designed cores, prevent the potential performance from being fully utilized. In this paper, we harness the mentioned side effects in shared-memory multicore processors with unknown workloads by a dynamic heuristic scheduling algorithm called HDSAP. HDSAP aims to maximize performance, i.e., the average response time, under power and reliability constraints in presence of induced heterogeneities. In this regard, we use a mathematical model to quantify task to core assignments based on performance variation. We also consider the variation in power to change selected cores when the power constraint is missed. To meet the reliability constraint, we use N-modular redundancy while being aware of the variation in the soft error rate of cores to prevent under/over reliability estimation. To evaluate HDSAP, we run SPLASH benchmark suite on Sniper and MACPat simulators. As a result, the response time of HDSAP reduces by 6%, 8%, and 25% in comparison with similar algorithms under the same power and reliability constraints.
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ISSN:0920-8542
1573-0484
DOI:10.1007/s11227-023-05159-6