Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis
This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a no...
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| Published in: | Wireless personal communications Vol. 127; no. 3; pp. 1869 - 1878 |
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| Main Authors: | , , |
| Format: | Journal Article |
| Language: | English |
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New York
Springer US
01.12.2022
Springer Nature B.V |
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| ISSN: | 0929-6212, 1572-834X |
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| Abstract | This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a novel high-level synthesis design method, which reduces pessimism associated with bit-width constraints in synthesis for inputs, outputs, and intermediate data nodes. MATLAB HDL coder generated Register Transfer Level (RTL) code was implemented on Xilinx Kintex 7 using Vivado software. The obtained results are superior to those of previous implementations for exact filter specifications. We also performed an RTL simulation for the filter and compared the functional verification results with a golden double-precision implementation in MATLAB. The results suggest that constraining the bit width and pessimism reduction has less than 1% impact on the filter accuracy within limits specified by architecture specifications. |
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| AbstractList | This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a novel high-level synthesis design method, which reduces pessimism associated with bit-width constraints in synthesis for inputs, outputs, and intermediate data nodes. MATLAB HDL coder generated Register Transfer Level (RTL) code was implemented on Xilinx Kintex 7 using Vivado software. The obtained results are superior to those of previous implementations for exact filter specifications. We also performed an RTL simulation for the filter and compared the functional verification results with a golden double-precision implementation in MATLAB. The results suggest that constraining the bit width and pessimism reduction has less than 1% impact on the filter accuracy within limits specified by architecture specifications. |
| Author | Shekhar, Chandra Sikka, Prateek Asati, Abhijit R. |
| Author_xml | – sequence: 1 givenname: Prateek surname: Sikka fullname: Sikka, Prateek email: prateeksikka@gmail.com organization: Electrical and Electronics Engineering Department, Birla Institute of Technology and Science – sequence: 2 givenname: Abhijit R. surname: Asati fullname: Asati, Abhijit R. organization: Electrical and Electronics Engineering Department, Birla Institute of Technology and Science – sequence: 3 givenname: Chandra surname: Shekhar fullname: Shekhar, Chandra organization: Electrical and Electronics Engineering Department, Birla Institute of Technology and Science |
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| Cites_doi | 10.1007/978-981-13-2119-1_77 10.1109/ICCCAS.2009.5250337 10.1007/s12204-020-2214-z 10.1109/INCCES47820.2019.9167696 10.1109/ICBSII49132.2020.9167598 10.1109/TCAD.2011.211059 10.1109/ASPCON49795.2020.9276711 |
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| Keywords | Hardware description language High-level synthesis Vivado DSP filter Field-programmable gate array MATLAB HDL coder Register transfer language |
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| References_xml | – reference: CongJLiuBNeuendorfferSNogueraJVissersKZhangZHigh-level synthesis for FPGAs: From prototyping to deploymentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems20113047349110.1109/TCAD.2011.211059 – reference: Sudharsan, R. R. (2019). Synthesis of FIR filter using ADC-DAC: A FPGA implementation. In 2019 IEEE international conference on clean energy and energy efficient electronics circuit for sustainable development (INCCES). IEEE. – reference: MathWorks HDL coder. https://www.mathworks.com/products/hdl-coder.html. – reference: Catapult® High-Level Synthesis. https://eda.sw.siemens.com/en-US/ic/ic-design/high-level-synthesis-and-verification-platform. Accessed 31 Mar 2021. – reference: WuTHigh-speed fault-tolerant finite impulse response digital filter on field programmable gate arrayJournal of Shanghai Jiaotong University (Science)202010.1007/s12204-020-2214-z – reference: Assef, A. A., et al. (2019). Modeling of a simple and efficient cascaded FPGA-based digital band-pass FIR filter for raw ultrasound data. In XXVI Brazilian congress on biomedical engineering. Singapore: Springer. – reference: QuayyumAMazherMDesign of programmable, efficient finite impulse response filter based on distributive arithmetic algorithmInternational Journal of Information Technology and Electrical Engineering201211924 – reference: Jose, J. P., Sundaram, M., & Jaffino, G. (2020). FPGA implementation of epileptic seizure detection using ELM classifier. In 2020 6th international conference on bio signals, images, and instrumentation (ICBSII), Chennai, India (pp. 1–5). https://doi.org/10.1109/ICBSII49132.2020.9167598. – reference: Xilinx. (2018). Vivado Design Suite: High-Level Synthesis. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug902-vivado-high-level-synthesis.pdf. – reference: Dutta, T., Aich, R. M., Dhabal, S., & Venkateswaran, P. (2020). Finite impulse response filterdesign using Grasshopper optimization algorithm and implementation on FPGA. In 2020 IEEE applied signal processing conference (ASPCON), Kolkata, India (pp. 313–317). https://doi.org/10.1109/ASPCON49795.2020.9276711. – reference: Synphony H-Level Synthesis. https://news.synopsys.com/index.php?s=20295&item=123096. Accessed 31 Mar 2021. – reference: SumanthKNagakishore BhavanamSBhaskara RaoBPerformance analysis of non-uniform filter bank with equi ripple bandpass filterSignal Processing201612 – reference: Ruan, A. W., Liao, Y. B., & Li, J. X. (2009). An ALU-based universal architecture for FIR filters. In IEEE proceedings of international conference on communications, circuits and systems, Milpitas, July 2009 (pp. 1070–1073). – reference: Stratus High-Level Synthesis. https://www.cadence.com/ko_KR/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html. Accessed 31 Mar 2021. – ident: 8727_CR5 doi: 10.1007/978-981-13-2119-1_77 – volume: 1 start-page: 2 year: 2016 ident: 8727_CR12 publication-title: Signal Processing – ident: 8727_CR9 – ident: 8727_CR1 doi: 10.1109/ICCCAS.2009.5250337 – year: 2020 ident: 8727_CR3 publication-title: Journal of Shanghai Jiaotong University (Science) doi: 10.1007/s12204-020-2214-z – ident: 8727_CR4 doi: 10.1109/INCCES47820.2019.9167696 – ident: 8727_CR13 doi: 10.1109/ICBSII49132.2020.9167598 – ident: 8727_CR7 – ident: 8727_CR6 – ident: 8727_CR10 – ident: 8727_CR11 – volume: 30 start-page: 473 year: 2011 ident: 8727_CR8 publication-title: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems doi: 10.1109/TCAD.2011.211059 – ident: 8727_CR14 doi: 10.1109/ASPCON49795.2020.9276711 – volume: 1 start-page: 19 year: 2012 ident: 8727_CR2 publication-title: International Journal of Information Technology and Electrical Engineering |
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| SubjectTerms | Bandpass filters Communications Engineering Computer Communication Networks Digital signal processing Engineering Field programmable gate arrays FIR filters High level synthesis Matlab Networks Signal,Image and Speech Processing Specifications |
| Title | Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis |
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