Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis

This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a no...

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Vydáno v:Wireless personal communications Ročník 127; číslo 3; s. 1869 - 1878
Hlavní autoři: Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York Springer US 01.12.2022
Springer Nature B.V
Témata:
Bandpass filters
Communications Engineering
Computer Communication Networks
Digital signal processing
Engineering
Field programmable gate arrays
FIR filters
High level synthesis
Matlab
Networks
Signal,Image and Speech Processing
Specifications
Hardware description language
High-level synthesis
Vivado
DSP filter
Field-programmable gate array
MATLAB HDL coder
Register transfer language
ISSN:0929-6212, 1572-834X
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Shrnutí:This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a novel high-level synthesis design method, which reduces pessimism associated with bit-width constraints in synthesis for inputs, outputs, and intermediate data nodes. MATLAB HDL coder generated Register Transfer Level (RTL) code was implemented on Xilinx Kintex 7 using Vivado software. The obtained results are superior to those of previous implementations for exact filter specifications. We also performed an RTL simulation for the filter and compared the functional verification results with a golden double-precision implementation in MATLAB. The results suggest that constraining the bit width and pessimism reduction has less than 1% impact on the filter accuracy within limits specified by architecture specifications.
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ISSN:0929-6212
1572-834X
DOI:10.1007/s11277-021-08727-2