APPAs: fast and efficient approximate parallel prefix adders and multipliers

In this paper, the approximate parallel prefix adders with minimizing hardware and timing complexities are proposed. Moreover, an approximate multiplier based on these adders is designed. The approximate structures include two approximate Sklansky adders, one approximate Ladner-Fischer adder, and on...

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Vydané v:	The Journal of supercomputing Ročník 80; číslo 16; s. 24269 - 24296
Hlavný autor:	Rashidi, Bahram
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York Springer US 01.11.2024 Springer Nature B.V
Predmet:	Accuracy Algorithms Approximation Compilers Computer Science Critical path Delay Design Errors Gate counting Hardware Image filters Image processing Interpreters Low pass filters Multiplication & division Multipliers Processing speed Processor Architectures Programming Languages Signal processing ASIC Approximate adder Parallel prefix adders (PPA) Imprecise image processing Approximate multiplier
ISSN:	0920-8542, 1573-0484
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