APPAs: fast and efficient approximate parallel prefix adders and multipliers
In this paper, the approximate parallel prefix adders with minimizing hardware and timing complexities are proposed. Moreover, an approximate multiplier based on these adders is designed. The approximate structures include two approximate Sklansky adders, one approximate Ladner-Fischer adder, and on...
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| Veröffentlicht in: | The Journal of supercomputing Jg. 80; H. 16; S. 24269 - 24296 |
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| Format: | Journal Article |
| Sprache: | Englisch |
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Springer US
01.11.2024
Springer Nature B.V |
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| ISSN: | 0920-8542, 1573-0484 |
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| Abstract | In this paper, the approximate parallel prefix adders with minimizing hardware and timing complexities are proposed. Moreover, an approximate multiplier based on these adders is designed. The approximate structures include two approximate Sklansky adders, one approximate Ladner-Fischer adder, and one approximate Kogge-Stone adder. The proposed adders are free from carry rippling. The main strategy for approximate design is primarily based on rearranging and deleting sub-blocks and secondary reducing the critical path delay and area in the adders. In this case, we have a trade-off between accuracy, delay, and area. The proposed approximate multiplier has a serial structure that is designed based on using one approximate parallel prefix adder. The proposed approximate adders and multiplier are compared from hardware and accuracy point of view such as gate count, delay, area delay product, error rate, mean error distance, mean relative error distance, and normalized error distance. The efficacy of proposed structures in image processing applications such as image smoothing (low-pass filter) and image multiplication is performed using MATLAB. The results show the proposed approximate structures are comparable in terms of area, delay, PSNR, and mean structural similarity index metric parameters with other works. |
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| AbstractList | In this paper, the approximate parallel prefix adders with minimizing hardware and timing complexities are proposed. Moreover, an approximate multiplier based on these adders is designed. The approximate structures include two approximate Sklansky adders, one approximate Ladner-Fischer adder, and one approximate Kogge-Stone adder. The proposed adders are free from carry rippling. The main strategy for approximate design is primarily based on rearranging and deleting sub-blocks and secondary reducing the critical path delay and area in the adders. In this case, we have a trade-off between accuracy, delay, and area. The proposed approximate multiplier has a serial structure that is designed based on using one approximate parallel prefix adder. The proposed approximate adders and multiplier are compared from hardware and accuracy point of view such as gate count, delay, area delay product, error rate, mean error distance, mean relative error distance, and normalized error distance. The efficacy of proposed structures in image processing applications such as image smoothing (low-pass filter) and image multiplication is performed using MATLAB. The results show the proposed approximate structures are comparable in terms of area, delay, PSNR, and mean structural similarity index metric parameters with other works. |
| Author | Rashidi, Bahram |
| Author_xml | – sequence: 1 givenname: Bahram surname: Rashidi fullname: Rashidi, Bahram email: b.rashidi@abru.ac.ir organization: Department of Electrical Engineering, Faculty of Engineering, Ayatollah Boroujerdi University |
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| CitedBy_id | crossref_primary_10_1016_j_asej_2025_103523 crossref_primary_10_1016_j_vlsi_2025_102522 crossref_primary_10_1016_j_rineng_2025_105783 crossref_primary_10_1016_j_sysarc_2025_103467 crossref_primary_10_1109_TCSI_2024_3511955 crossref_primary_10_1016_j_vlsi_2025_102344 crossref_primary_10_1080_1448837X_2025_2454812 crossref_primary_10_1109_TCSI_2024_3509013 crossref_primary_10_1016_j_rineng_2024_103798 crossref_primary_10_1016_j_vlsi_2024_102317 |
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| Keywords | ASIC Approximate adder Parallel prefix adders (PPA) Imprecise image processing Approximate multiplier |
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| SubjectTerms | Accuracy Algorithms Approximation Compilers Computer Science Critical path Delay Design Errors Gate counting Hardware Image filters Image processing Interpreters Low pass filters Multiplication & division Multipliers Processing speed Processor Architectures Programming Languages Signal processing |
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| Title | APPAs: fast and efficient approximate parallel prefix adders and multipliers |
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