A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design
In electronic design automation, hardware/software co-design significantly reduces the time-to-market and improves the performance of embedded systems. With the increasing scale of applications and complexity of hardware architecture of embedded systems, hardware/software co-design is still a resear...
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| Vydané v: | Design automation for embedded systems Ročník 23; číslo 1-2; s. 57 - 77 |
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| Hlavní autori: | , , |
| Médium: | Journal Article |
| Jazyk: | English |
| Vydavateľské údaje: |
New York
Springer US
15.06.2019
Springer Nature B.V |
| Predmet: | |
| ISSN: | 0929-5585, 1572-8080 |
| On-line prístup: | Získať plný text |
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| Shrnutí: | In electronic design automation, hardware/software co-design significantly reduces the time-to-market and improves the performance of embedded systems. With the increasing scale of applications and complexity of hardware architecture of embedded systems, hardware/software co-design is still a research hotspot. As hardware/software co-design is a wide topic, this paper focuses on major developments of three important aspects related to hardware/software partitioning, which has great effects on the performance of embedded systems. Firstly, various partitioning models including hardware architectures and abstract models are surveyed. Secondly, classical and new algorithms for hardware/software partitioning are classified and analyzed. Thirdly, existing parallel algorithms for hardware/software co-design are discussed in details. Finally, possible research directions are pointed out in conclusion. |
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| Bibliografia: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ISSN: | 0929-5585 1572-8080 |
| DOI: | 10.1007/s10617-019-09220-7 |