Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices

This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we sugge...

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Bibliographic Details
Published in:Neural computing & applications Vol. 19; no. 2; pp. 283 - 297
Main Authors: Boubaker, Mohamed, Akil, Mohamed, Ben Khalifa, Khaled, Grandpierre, Thierry, Bedoui, Mohamed Hedi
Format: Journal Article
Language:English
Published: London Springer-Verlag 01.03.2010
Springer
Subjects:
Applied sciences
Artificial Intelligence
Combinatorics
Combinatorics. Ordered structures
Computational Biology/Bioinformatics
Computational Science and Engineering
Computer Science
Computer science; control theory; systems
Data Mining and Knowledge Discovery
Designs and configurations
Exact sciences and technology
Experimental design
Image Processing and Computer Vision
Inference from stochastic processes; time series analysis
Learning and adaptive systems
Mathematics
Original Article
Probability and statistics
Probability and Statistics in Computer Science
Sciences and techniques of general use
Statistics
FPGA implementation
Rapid prototyping
Co-design methodology
Variable size LVQ
Heuristics
Optimization
Human
Vigilance
Neural computation
Architecture
Methodology
Vector quantization
Algorithmics
Field programmable gate array
Specification
Neural network
Real time
Algorithm
Implementation
Learning
Generation
Software tool
Experimental design
Classification
Neural circuit
Application
ISSN:0941-0643, 1433-3058
Online Access:Get full text
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Summary:This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we suggest a design methodology of the LVQ-dedicated architecture. This formal methodology is called AAA, “Algorithm Architecture Adequation”. Using graph transformations, it allows the generation of an optimized circuit implementation at the Register Transfer Level (RTL). It is associated to the SynDEx-IC software tool. Based on this formal methodology, we are able to explore and generate various LVQ network implementations by varying the LVQ sizes while minimizing the hardware resources and the design time. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized LVQ implementation was tried on two types of Virtex devices.
ISSN:0941-0643
1433-3058
DOI:10.1007/s00521-009-0296-5