Modeling of Doped Fully Depleted Behavior Induced by Total Ionizing Dose in Voltage Reference Circuits From a 65-nm Partially Depleted SOI Technology

In this article, a doped fully depleted silicon on insulator (FDSOI) behavior for the 65-nm partially depleted silicon on insulator (PDSOI) technology is demonstrated to understand the output voltage shift of a voltage reference (VR) undergoing dose deposition in real time. From an in-depth top-bott...

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Veröffentlicht in:IEEE transactions on nuclear science Jg. 72; H. 4; S. 1276 - 1284
Hauptverfasser: Lomonaco, J., Rostand, N., Martinie, S., Charbonnier, G., Marcandella, C., Bedecarrats, T., Bournel, A.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.04.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
CAD
Circuits
Computer aided design
Degradation
Depletion
Doping
Fully depleted silicon on insulator (FDSOI)
Integrated circuit modeling
Integrated circuits
modeling
Multiscale analysis
partially depleted silicon on insulator (PDSOI)
Photonic band gap
Predictive models
radiation experiments
Semiconductor process modeling
Silicon
Silicon-on-insulator
simulation program with integrated circuit emphasis (SPICE) simulation
SOI (semiconductors)
technology computer aided design (TCAD)
Threshold voltage
Total ionizing dose
total ionizing dose (TID)
Transistors
Voltage
voltage reference (VR)
ISSN:0018-9499, 1558-1578
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Zusammenfassung:In this article, a doped fully depleted silicon on insulator (FDSOI) behavior for the 65-nm partially depleted silicon on insulator (PDSOI) technology is demonstrated to understand the output voltage shift of a voltage reference (VR) undergoing dose deposition in real time. From an in-depth top-bottom analysis, including both experiments and technology computer aided design (TCAD)/simulation program with integrated circuit emphasis (SPICE) simulations, we highlighted this unexpected doped FDSOI behavior. This study shows how it worsens the total ionizing dose (TID) effects due to the coupling effect between the front and back interfaces, not usual in this technology. A new threshold voltage model considering channel doping and TID is developed, showing how doping concentration is an important hardening parameter. This model is reused, in a multiscale approach, to reproduce the output voltage shift of a VR based on the PDSOI transistor degradation.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2025.3531687