AEQUAM: Accelerating Quantum Algorithm Validation Through FPGA-Based Emulation

This work presents AEQUAM (Area Efficient QUAntum eMulation), a toolchain that enables faster and more accessible quantum circuit verification. It consists of a compiler that translates OpenQASM 2.0 into RISC-like instructions, Cython software models for selecting number representations and simulati...

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Veröffentlicht in:	IEEE access Jg. 13; S. 130232 - 130255
Hauptverfasser:	Lagostina, Lorenzo, Volpe, Deborah, Zamboni, Maurizio, Turvani, Giovanna
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Piscataway IEEE 2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Computer architecture Emulation Emulators field programmable gate array Field programmable gate arrays Hardware description languages Logic gates Quantum algorithm quantum algorithm verification Quantum circuit Quantum computing Quantum computing emulation quantum computing simulation Quantum mechanics Quantum state Qubit Qubits (quantum computing) Representations User requirements Vectors
ISSN:	2169-3536, 2169-3536
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Abstract	This work presents AEQUAM (Area Efficient QUAntum eMulation), a toolchain that enables faster and more accessible quantum circuit verification. It consists of a compiler that translates OpenQASM 2.0 into RISC-like instructions, Cython software models for selecting number representations and simulating circuits, and a VHDL generator that produces RTL descriptions for FPGA-based hardware emulators. The architecture leverages a SIMD approach to parallelize computation and reduces complexity by exploiting the sparsity of quantum gate matrices. The VHDL generator allows customization of the number of emulated qubits and parallelization levels to meet user requirements. Synthesized on an Altera Cyclone 10LP FPGA with a 20-bit fixed-point representation and nearest-type approximation, the architecture demonstrates better scalability than other state-of-the-art emulators. Specifically, the emulator has been validated by exploiting the well consolidated benchmark of mqt bench framework.
AbstractList	This work presents AEQUAM (Area Efficient QUAntum eMulation), a toolchain that enables faster and more accessible quantum circuit verification. It consists of a compiler that translates OpenQASM 2.0 into RISC-like instructions, Cython software models for selecting number representations and simulating circuits, and a VHDL generator that produces RTL descriptions for FPGA-based hardware emulators. The architecture leverages a SIMD approach to parallelize computation and reduces complexity by exploiting the sparsity of quantum gate matrices. The VHDL generator allows customization of the number of emulated qubits and parallelization levels to meet user requirements. Synthesized on an Altera Cyclone 10LP FPGA with a 20-bit fixed-point representation and nearest-type approximation, the architecture demonstrates better scalability than other state-of-the-art emulators. Specifically, the emulator has been validated by exploiting the well consolidated benchmark of mqt bench framework.
Author	Turvani, Giovanna Volpe, Deborah Lagostina, Lorenzo Zamboni, Maurizio
Author_xml	– sequence: 1 givenname: Lorenzo orcidid: 0009-0004-7720-8202 surname: Lagostina fullname: Lagostina, Lorenzo organization: Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy – sequence: 2 givenname: Deborah orcidid: 0000-0003-3364-1114 surname: Volpe fullname: Volpe, Deborah organization: Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy – sequence: 3 givenname: Maurizio orcidid: 0000-0001-8179-5973 surname: Zamboni fullname: Zamboni, Maurizio organization: Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy – sequence: 4 givenname: Giovanna orcidid: 0000-0002-8520-906X surname: Turvani fullname: Turvani, Giovanna email: giovanna.turvani@polito.it organization: Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy
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SubjectTerms	Computer architecture Emulation Emulators field programmable gate array Field programmable gate arrays Hardware description languages Logic gates Quantum algorithm quantum algorithm verification Quantum circuit Quantum computing Quantum computing emulation quantum computing simulation Quantum mechanics Quantum state Qubit Qubits (quantum computing) Representations User requirements Vectors
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Title	AEQUAM: Accelerating Quantum Algorithm Validation Through FPGA-Based Emulation
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