Fault Analysis-Based Logic Encryption

Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately 4 billion annually. One way to protect ICs from these...

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Vydané v:IEEE transactions on computers Ročník 64; číslo 2; s. 410 - 424
Hlavní autori: Rajendran, Jeyavijayan, Zhang, Huan, Zhang, Chi, Rose, Garrett S., Pino, Youngok, Sinanoglu, Ozgur, Karri, Ramesh
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.02.2015
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Automatic test pattern generation
Circuit faults
combinational logic circuit
Design engineering
Encryption
Faults
Foundries
Gates (circuits)
Hardware
hardware security
IC piracy
Inserts
integrated circuit testing
Integrated circuits
IP piracy
Logic
Logic gates
logic obfuscation
Supply chains
Testing
ISSN:0018-9340, 1557-9956
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Shrnutí:Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately 4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design, but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
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ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2013.193