Field-Programmable Gate Array Implementation of Backprojection Algorithm for Circular Synthetic Aperture Radar

This paper presents a backprojection algorithm (BPA) accelerator implemented on a field-programmable gate array (FPGA) for circular synthetic aperture radar (SAR) systems. Although the BPA offers superior image quality, it requires significantly more computation and is memory intensive, necessitatin...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Electronics (Basel) Jg. 14; H. 8; S. 1544
Hauptverfasser: Heo, Jinmoo, Lee, Seongjoo, Jung, Yunho
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Basel MDPI AG 10.04.2025
Schlagworte:
Aircraft
Algorithms
Antennas
Artificial satellites in remote sensing
Computation
Digital integrated circuits
Efficiency
Embedded systems
Field programmable gate arrays
Floating point arithmetic
Fourier transforms
Ground stations
Image quality
Optimization
Radar
Signal processing
Synthetic aperture radar
United States
ISSN:2079-9292, 2079-9292
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper presents a backprojection algorithm (BPA) accelerator implemented on a field-programmable gate array (FPGA) for circular synthetic aperture radar (SAR) systems. Although the BPA offers superior image quality, it requires significantly more computation and is memory intensive, necessitating hardware optimization. In particular, the BPA accumulates image data, leading to high memory requirements that must be reduced for embedded system implementation. To address this issue, we optimized the floating-point (FP) bit width, focusing on the output data that form the image, rather than only reducing the internal computation bit widths as in previous studies. Specifically, we optimized the exponent and mantissa widths in six computational units, prioritizing memory optimization for image data before reducing the computational logic. The proposed BPA accelerator achieved a 77% reduction in memory usage and a 73–74% reduction in computational logic while maintaining an image quality with a structural similarity index measure (SSIM) of 0.99 or higher. These optimizations significantly enhanced the feasibility of BPA processing in embedded systems.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics14081544