RESETting Timed Machines
Many real-time applications enable RESET to account for all kinds of unexpected problems, or to accommodate for a users' want of restarting. Additionally, some software testing techniques must allow for RESETting timed-Implementations Under Test (t-IUT). Dedicated internal logic is probably the...
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| Veröffentlicht in: | Journal of computing and information technology Jg. 19; H. 1; S. 11 - 23 |
|---|---|
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| Format: | Journal Article Paper |
| Sprache: | Englisch |
| Veröffentlicht: |
Zagreb
University Computing Centre
01.03.2011
Sveuciliste U Zagrebu Fakultet elektrotehnike i računarstva Sveučilišta u Zagrebu |
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| ISSN: | 1330-1136, 1846-3908 |
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| Abstract | Many real-time applications enable RESET to account for all kinds of unexpected problems, or to accommodate for a users' want of restarting. Additionally, some software testing techniques must allow for RESETting timed-Implementations Under Test (t-IUT). Dedicated internal logic is probably the most common of solutions for accomplishing such tasks. There are situations, however, where such a privilege doesn't exist; thus, it cannot be built upon. Testing pre-engineered timed-IUTs is one such case. In this paper we wish to present an algorithm for the direct generation of timed RESET sequences from the timed-IUT specification, such that it should be optimal w.r.t. to execution time. |
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| AbstractList | Many real-time applications enable RESET to account for all kinds of unexpected problems, or to accommodate for a users' want of restarting. Additionally, some software testing techniques must allow for RESETting timed-Implementations Under Test (t-IUT). Dedicated internal logic is probably the most common of solutions for accomplishing such tasks. There are situations, however, where such a privilege doesn't exist; thus, it cannot be built upon. Testing pre-engineered timed-IUTs is one such case. In this paper we wish to present an algorithm for the direct generation of timed RESET sequences from the timed-IUT specification, such that it should be optimal w.r.t. to execution time. Keywords: D.2.4 [Software Engineering]: Software/Program Verification--Formal Methods; F.1.1 [Theory of Computation]: Models of Computations--Automata; D.2.m [Software Engineering]: Miscellaneous--Realtime systems Many real-time applications enable RESET to account for all kinds of unexpected problems, or to accommodate for a users' want of restarting. Additionally, some software testing techniques must allow for RESETting timed-Implementations Under Test (t-IUT). Dedicated internal logic is probably the most common of solutions for accomplishing such tasks. There are situations, however, where such a privilege doesn't exist; thus, it cannot be built upon. Testing pre-engineered timed-IUTs is one such case. In this paper we wish to present an algorithm for the direct generation of timed RESET sequences from the timed-IUT specification, such that it should be optimal w.r.t. to execution time. |
| Audience | Academic |
| Author | Stulman, Ariel |
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| Snippet | Many real-time applications enable RESET to account for all kinds of unexpected problems, or to accommodate for a users' want of restarting. Additionally, some... Many real-time applications enable RESET to account for all kinds of unexpected problems, or to accommodate for a users’ want of restarting. Additionally, some... |
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| StartPage | 11 |
| SubjectTerms | Algorithms Applied sciences automata Computer science; control theory; systems Computer systems performance. Reliability Exact sciences and technology formal methods models of computations realtime systems Robots Software Software engineering software/program verification |
| Title | RESETting Timed Machines |
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