RESETting Timed Machines

Many real-time applications enable RESET to account for all kinds of unexpected problems, or to accommodate for a users' want of restarting. Additionally, some software testing techniques must allow for RESETting timed-Implementations Under Test (t-IUT). Dedicated internal logic is probably the...

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Bibliographic Details
Published in:Journal of computing and information technology Vol. 19; no. 1; pp. 11 - 23
Main Author: Stulman, Ariel
Format: Journal Article Paper
Language:English
Published: Zagreb University Computing Centre 01.03.2011
Sveuciliste U Zagrebu
Fakultet elektrotehnike i računarstva Sveučilišta u Zagrebu
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ISSN:1330-1136, 1846-3908
Online Access:Get full text
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Summary:Many real-time applications enable RESET to account for all kinds of unexpected problems, or to accommodate for a users' want of restarting. Additionally, some software testing techniques must allow for RESETting timed-Implementations Under Test (t-IUT). Dedicated internal logic is probably the most common of solutions for accomplishing such tasks. There are situations, however, where such a privilege doesn't exist; thus, it cannot be built upon. Testing pre-engineered timed-IUTs is one such case. In this paper we wish to present an algorithm for the direct generation of timed RESET sequences from the timed-IUT specification, such that it should be optimal w.r.t. to execution time.
Bibliography:67546
ISSN:1330-1136
1846-3908
DOI:10.2498/cit.1001762