Force-directed algorithms for schematic drawings and placement: A survey

Force-directed algorithms have been developed over the last 50 years and used in many application fields, including information visualisation, biological network visualisation, sensor networks, routing algorithms, scheduling, and graph drawing. Our survey provides a comprehensive summary of developm...

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Veröffentlicht in:Information visualization Jg. 19; H. 1; S. 65 - 91
Hauptverfasser: Cheong, Se-Hang, Si, Yain-Whar
Format: Journal Article
Sprache:Englisch
Veröffentlicht: London, England SAGE Publications 01.01.2020
SAGE PUBLICATIONS, INC
Schlagworte:
Algorithms
Circuit design
Circuits
Combinatorial analysis
Domains
Energy conservation
High level synthesis
Localization
Measures
Networks
Optimization
Placement
Polls & surveys
Scheduling
Very large scale integration
Visualization
force-directed placement
schematic drawing
Force-directed algorithms
information visualisation
ISSN:1473-8716, 1473-8724
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Zusammenfassung:Force-directed algorithms have been developed over the last 50 years and used in many application fields, including information visualisation, biological network visualisation, sensor networks, routing algorithms, scheduling, and graph drawing. Our survey provides a comprehensive summary of developments and a full roadmap for state-of-the-art force-directed algorithms in schematic drawings and placement. We classified the model of force-directed algorithms into classical and hybrid. The classical force-directed algorithms are further classified as follows: (a) accumulated force models, (b) energy function minimisation models and (c) combinatorial optimisation models. The hybrid force-directed algorithms are classified as follows: (a) parallel and hardware accelerated models, (b) multilevel force-directed models and (c) multidimensional scaling force-directed algorithms. Five categories of application domains in which force-directed algorithms have been adopted for schematic drawings and placement are also summarised: (a) aesthetic drawings for general networks, (b) component placement and scheduling in high-level synthesis of very-large-scale integration circuits design, (c) information visualisation, (d) biological network visualisation and (e) node placement and localisation for sensor networks.
Bibliographie:ObjectType-Article-1
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ISSN:1473-8716
1473-8724
DOI:10.1177/1473871618821740