Design of self-testable wafer-scale processor arrays

A technique for designing self-testable wafer-scale arrays is presented. Faulty and Fault-free cells (processors, PEs) are indentified in distributed fashion without providing correct responses from the outside. It uses both local comparisons and dissemination of the comparison results. Faults in di...

Full description

Bibliographic Details

Published in:	International journal of electronics Vol. 69; no. 5; pp. 665 - 671
Main Author:	CHOI, YOON-HWA
Format:	Journal Article
Language:	English
Published:	London Taylor & Francis Group 01.11.1990 Taylor & Francis
Subjects:	Applied sciences Electronics Exact sciences and technology Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Processor Circuit design Test Network Defect Algorithm Wafer
ISSN:	0020-7217, 1362-3060
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!