Design of self-testable wafer-scale processor arrays

A technique for designing self-testable wafer-scale arrays is presented. Faulty and Fault-free cells (processors, PEs) are indentified in distributed fashion without providing correct responses from the outside. It uses both local comparisons and dissemination of the comparison results. Faults in di...

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Bibliographic Details
Published in:International journal of electronics Vol. 69; no. 5; pp. 665 - 671
Main Author: CHOI, YOON-HWA
Format: Journal Article
Language:English
Published: London Taylor & Francis Group 01.11.1990
Taylor & Francis
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Processor
Circuit design
Test
Network
Defect
Algorithm
Wafer
ISSN:0020-7217, 1362-3060
Online Access:Get full text
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Summary:A technique for designing self-testable wafer-scale arrays is presented. Faulty and Fault-free cells (processors, PEs) are indentified in distributed fashion without providing correct responses from the outside. It uses both local comparisons and dissemination of the comparison results. Faults in diagnostic circuits, which have been typically assumed to be fault-free, are also covered by the self-testing algorithm. The algorithm is quite general in the sense that it is independent of the structure of the syndrome analyser in each cell.
Bibliography:ObjectType-Article-2
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ISSN:0020-7217
1362-3060
DOI:10.1080/00207219008920353